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Electronique embarquée [Embedded Electronics] (BEAMSEE)
Faculté des Sciences appliquées - école polytechnique / Brussels School of Engineering (Faculty of Applied Sciences) - Electromécanique (unité ULB669)

L'unité de recherche 'Electronique Embarquée' centre ses activités sur la conception et l'implémentation de systémes embarqués. L'expertise qu'elle offre repose sur la maétrise de disciplines variées, parmi lesquelles: l'électronique/microlectronique numérique (architectures classiques ou avancées: microprocesseurs, FPGAs, DSPs, MPSoCs, NoCs, etc); l'instrumentation (acquisition de données, capteurs, etc); et la maétrise des systémes temps réel (OS temps réel, bus de terrain, etc). En termes d'applications, l'unité de recherche dispose d'une solide expérience dans le contréle-commande d'équipements de puissance (convertisseurs d'électronique de puissance, moteurs électriques, etc), le traitement d'images, ainsi que les systémes de mesure ou de contréle pour applications biomédicales (monitoring, anesthésie, etc). L'unité de recherche développe également des activités originales dans le domaine de l'étude des processus d'apprentissage (réalisés par des humains ou par des machines: intelligence artificielle), activités qui sont notamment mises A  profit dans la conception de systémes embarqués adaptatifs ou cognitifs (c'est-A -dire capables d'apprentissage). [The 'Embedded Electronics' research unit offers expertise in the field of design and implementation of embedded systems. This work relies on various core disciplines, mainly: digital electronics and microelectronics on classical or advanced architectures (processors, microcontrollers, DSPs, FPGAs, MPSOCs, Network-on-Chips, etc); instrumentation (data acquisition, sensors, etc); and management of real-time constraints (real-time operating systems, field buses, etc). In terms of applications, our main background concerns the domains of: power electronics control, image processing and biomedical measurement and control systems. Studying the learning process, performed by humans as well as by machines, is another of our key activities. It articulates to the previous applications when considering adaptive and/or cognitive artificial systems.]



coordonnées / contact details


Electronique embarquée [Embedded Electronics]
tel +32-2-650.30.60, fax +32-2-650.24.82, frrobert@ulb.ac.be
http://beams.ulb.ac.be/ee/intro.html
Campus du Solbosch, Bâtiment U, porte A, niveau 2
CP165/56, avenue F.D. Roosevelt 50, 1050 Bruxelles

Pour en savoir plus, consultez le site web de l'unité.



responsable / head


Prof. Frédéric ROBERT


composition / members


Emmanuel BAIRY Kevin DE CUYPER Axel DERO Anthony LEROY Pierre MATHYS Dragomir MILOJEVIC Geoffrey NELISSEN Michel OSEE Vincent RAMAN Aliénor RICHARD


projets / projects


PowPLAT: Plateforme de commande numérique de convertisseurs d'électronique de puissance
Réalisation d'une plateforme didactique, polyvalente et modulaire de commande numérique de convertisseurs d'électronique de puissance. Cette plateforme sera A  terme utilisée dans le cadre de laboratoires de Génie Electrique. Elle sera également exploitée par différents chercheurs et doctorants comme environnement de test et de validation des résultats de leur recherche.

VIENNA: Realisation d'un maquette de PFC triphasé basse puissance
Réalisation d'une maquette basse puissance d'un redresseur triphasé VIENNA et implémentation d'une commande vectorielle sur le DSP F2812 de Texas Instruments.

Digital Sliding Mode [Digital Sliding Mode]

CONVER2020

Hardware services for MPSoC with real-time operating systems [Hardware services for MPSoC with real-time operating systems]
In recent years we have witnessed a paradigm shift in computer systems. Increasing the frequency has given way to multi-core architectures exploiting the parallelism. In the field of embedded systems, such a vision is seen in the form of Multi-Processor System-on-Chip - MPSoC. The advantages of such a platform in comparison with a uni-processor one are multiples in several domains like power consumption, scalability and reusability. In the same time, a lot of existing systems need Real Time Operating Systems not only to guarantee a given treatment capacity but also to guarantee a deadline for multiple tasks. To break with the sub-optimality of the actual philosophy consisting to see the design of software and hardware as two worlds apart, the aim of this thesis is, through a co-design methodology, to design a configurable MPSoC environment with services tailored directly for high level real-time scheduling algorithms. [In recent years we have witnessed a paradigm shift in computer systems. Increasing the frequency has given way to multi-core architectures exploiting the parallelism. In the field of embedded systems, such a vision is seen in the form of Multi-Processor System-on-Chip - MPSoC. The advantages of such a platform in comparison with a uni-processor one are multiples in several domains like power consumption, scalability and reusability. In the same time, a lot of existing systems need Real Time Operating Systems not only to guarantee a given treatment capacity but also to guarantee a deadline for multiple tasks. To break with the sub-optimality of the actual philosophy consisting to see the design of software and hardware as two worlds apart, the aim of this thesis is, through a co-design methodology, to design a configurable MPSoC environment with services tailored directly for high level real-time scheduling algorithms.]

Outils d'estimation de performance multi-critére pour la conception électronique/microélectronique [Multi-criteria performance estimation tools for electronics/microelectronics design]
Phase 1 : la premiére phase du projet a consisté en l'analyse et le développement d'un outil original, Nessie, capable d'explorer simultanément les aspects applications et architectures d'un systéme-on-chip A  travers l'estimation de plusieurs critéres selon les besoins du concepteur. Cet outil se place en amont d'un flot top-down classique et permet de guider la conception d'un SoC en fournissant au niveau d'abstraction System-Level les solutions les plus pertinentes A  considérer. Phase 2 : la seconde phase consiste en la validation de l'outil A  travers des cas de conception réels. [Phase 1: the first phase consists in the analysis and the development of an original tool, called Nessie, able to simultaneously explore application and architecture aspects of a SoC through a multi-criteria performance estimation according to designer needs. This tool is used as an entry point to a classical top-down flow and enable to guide the design by giving relevant solutions to high abstraction levels. Phase 2: the second phase consists in the validation of the tool through real case studies.]

Pathfinding [Pathfinding: Design Methodologies and Tools for Efficient Design of 3D-Stacked Integrated Circuits]
In recent years, the industry focus has been put on 3D technology as it provides numerous opportunities for building better systems. The number of functions in the system can be extended beyond the near term capabilities of traditional 2D scaling. 3D resolves the interconnect performance limitations because long lateral wires can be replaced with much shorter connections, significantly reducing related RC delay and buffering cost. 3D integration also supports the heterogeneous integration of components in dedicated technologies improving performance/power/cost metrics. Besides classical system-level design challenges, 3D design also involves additional degrees of freedom: 1. Partitioning of the design across multiple tiers; e.g., RF on logic; DRAM on logic, MEMS on logic, etc.; use of an existing die vs. a new die; 2. Selection of process technology per tier; DRAM vs. CMOS, CMOS65 vs. CMOS45, etc.; 3. The choice of the 3D interconnect. A substantial variety of 3D-Stacked Integrated Circuits (3D-SICs) schemes have been proposed. Variations across different schemes occur in terms of via geometry and pitch, via pitch, via stacking method (face-to-face or back-to-face), and bonding method (e.g., oxide bonding vs. fusion bonding). Different stacking schemes imply different electrical characteristics for the 3D interconnects. In this work we develop new design methodology and the corresponding EDA tool chain enabling fast design space exploration for emerging heterogeneous 3D-SICs using Through Silicon Vias (TSV) for inter-die connexions. The proposed framework, called PATHFINDING FLOW, allow designers to quickly evaluate many trade-offs between different system level design choices (e.g. functional partitioning, micro-architecture configuration of the functional blocks, interconnect topology and configuration etc.), physical design options (e.g. packaging strategies) and/or technology options (e.g. different technology nodes, threshold voltages, etc.) and understand their impact on typical design parameters such as cost, performance and power. The proposed framework is based on existing state-of-the-art System Level Exploration tools, High-Level Synthesis (HLS) tools (for both processing and communication) and Virtual Prototyping. Different tools have been integrated in one, unique and automated environment. The resulting framework allows fast, accurate and iterative design space exploration, using feedbacks from lower to higher abstraction layers and enabling physical design parameters to influence the system level design choices. [In recent years, the industry focus has been put on 3D technology as it provides numerous opportunities for building better systems. The number of functions in the system can be extended beyond the near term capabilities of traditional 2D scaling. 3D resolves the interconnect performance limitations because long lateral wires can be replaced with much shorter connections, significantly reducing related RC delay and buffering cost. 3D integration also supports the heterogeneous integration of components in dedicated technologies improving performance/power/cost metrics. Besides classical system-level design challenges, 3D design also involves additional degrees of freedom: 1. Partitioning of the design across multiple tiers; e.g., RF on logic; DRAM on logic, MEMS on logic, etc.; use of an existing die vs. a new die; 2. Selection of process technology per tier; DRAM vs. CMOS, CMOS65 vs. CMOS45, etc.; 3. The choice of the 3D interconnect. A substantial variety of 3D-Stacked Integrated Circuits (3D-SICs) schemes have been proposed. Variations across different schemes occur in terms of via geometry and pitch, via pitch, via stacking method (face-to-face or back-to-face), and bonding method (e.g., oxide bonding vs. fusion bonding). Different stacking schemes imply different electrical characteristics for the 3D interconnects. In this work we develop new design methodology and the corresponding EDA tool chain enabling fast design space exploration for emerging heterogeneous 3D-SICs using Through Silicon Vias (TSV) for inter-die connexions. The proposed framework, called PATHFINDING FLOW, allow designers to quickly evaluate many trade-offs between different system level design choices (e.g. functional partitioning, micro-architecture configuration of the functional blocks, interconnect topology and configuration etc.), physical design options (e.g. packaging strategies) and/or technology options (e.g. different technology nodes, threshold voltages, etc.) and understand their impact on typical design parameters such as cost, performance and power. The proposed framework is based on existing state-of-the-art System Level Exploration tools, High-Level Synthesis (HLS) tools (for both processing and communication) and Virtual Prototyping. Different tools have been integrated in one, unique and automated environment. The resulting framework allows fast, accurate and iterative design space exploration, using feedbacks from lower to higher abstraction layers and enabling physical design parameters to influence the system level design choices.]

MacDO: Methodology for avionics certification for DO254 [MacDO: Methodology for avionics certification for DO254]
Ce projet traite de la certification avionique des composants Hardware. Cette étude est réalisée dans le cadre du projet CEIQS Recherche TIC. Le programme de recherche consiste dans un premier temps A  constituer une base de connaissance solide en matiére de certification aéronautique. La premiére période d'activité est consacrée A  la réalisation d'un état de l'art approfondi en matiére de certification. Le chercheur s'est donc intéressé principalement à l'étude des normes DO-178B relative à l'aspect logiciel, DO-254 pour l'aspect matériel et ARP4754 pour l'intégration systéme. (Le Fonds Européen de Développement Régional et la Région Wallonne investissent dans votre avenir) [This project is targeting avionics certification with a special focus on hardware components. This study is realized in the context of the CEIQS/Recherche TIC project. As a first step, the research program consists in building a strong knowledge base in avionics certification. The first activity consists in realizing a deep state of the art. The researcher thus mainly targeted the DO-178B standard for the software part and DO-254 for the hardware and finally ARP-4754 for system integration. (Le Fonds Européen de Développement Régional et la Région Wallonne investissent dans votre avenir)]



publications





theses


Developing multi-criteria performance estimation tools for System-on-Chips, 2009

Optimizing the on-chip communication architecture of low power Systems-on-Chip in Deep Sub-Micron technology, 2006

Implémentation des filtres non-linéaires de rang sur des architectures universelles et reconfigurables, 2004

Modélisation et simulation de transformateurs pour alimentations à découpage, 1999



collaborations


Prof. Verkest, Interuniversitair Microelectronics Center - IMEC, Digital Design Technology division, Leuven, Belgique

Prof. Tatakis, University of Patras, Electrical Engineering, Patras, Grèce

GREPES, Power Electronics for Severe Environment Research Group, Namur, Belgique



prix / awards


Prix ''Recherche et Développement 1995'' de la S.R.B.E. (Société Royale Belge des Electriciens) pour le travail de fin d'études ''Utilisation d'un système d'exploitation temps réel pour la supervision d'armoires d'alimentation'' - Frédéric ROBERT

Prix Socrate 2006 (ULB) récompensant ''des membres du corps enseignant de l'Université Libre de Bruxelles qui se distinguent particulièrement par la qualité de leur enseignement, par leur créativité et leur investissement dans le domaine didactique ainsi que par leur écoute de l'étudiant'' - Frédéric ROBERT



savoir-faire/équipements / know-how, equipment


Design and implementation of embedded systems: digital design on classical or advanced architectures (processors, microcontrollers, DSPs, FPGAs, MPSOCs, Network-on-Chips, etc); instrumentation (data acquisition, sensors, etc); management of real-time constraints (real-time operating systems, field buses, etc).



mots clés pour non-spécialistes / keywords for non-specialists


électronique instrumentation microélectronique systèmes embarqués systèmes sur puce


disciplines et mots clés / disciplines and keywords


Electronique et électrotechnique

electronique/microélectronique electronique de puissance gestion des ressources


codes technologiques DGTRE


Électronique Instrumentation Micro-électronique Sciences de l'ordinateur, analyse numérique, systèmes, contrôle Traitement des signaux