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Pathfinding [Pathfinding: Design Methodologies and Tools for Efficient Design of 3D-Stacked Integrated Circuits]

In recent years, the industry focus has been put on 3D technology as it provides numerous opportunities for building better systems. The number of functions in the system can be extended beyond the near term capabilities of traditional 2D scaling. 3D resolves the interconnect performance limitations because long lateral wires can be replaced with much shorter connections, significantly reducing related RC delay and buffering cost. 3D integration also supports the heterogeneous integration of components in dedicated technologies improving performance/power/cost metrics. Besides classical system-level design challenges, 3D design also involves additional degrees of freedom: 1. Partitioning of the design across multiple tiers; e.g., RF on logic; DRAM on logic, MEMS on logic, etc.; use of an existing die vs. a new die; 2. Selection of process technology per tier; DRAM vs. CMOS, CMOS65 vs. CMOS45, etc.; 3. The choice of the 3D interconnect. A substantial variety of 3D-Stacked Integrated Circuits (3D-SICs) schemes have been proposed. Variations across different schemes occur in terms of via geometry and pitch, via pitch, via stacking method (face-to-face or back-to-face), and bonding method (e.g., oxide bonding vs. fusion bonding). Different stacking schemes imply different electrical characteristics for the 3D interconnects. In this work we develop new design methodology and the corresponding EDA tool chain enabling fast design space exploration for emerging heterogeneous 3D-SICs using Through Silicon Vias (TSV) for inter-die connexions. The proposed framework, called PATHFINDING FLOW, allow designers to quickly evaluate many trade-offs between different system level design choices (e.g. functional partitioning, micro-architecture configuration of the functional blocks, interconnect topology and configuration etc.), physical design options (e.g. packaging strategies) and/or technology options (e.g. different technology nodes, threshold voltages, etc.) and understand their impact on typical design parameters such as cost, performance and power. The proposed framework is based on existing state-of-the-art System Level Exploration tools, High-Level Synthesis (HLS) tools (for both processing and communication) and Virtual Prototyping. Different tools have been integrated in one, unique and automated environment. The resulting framework allows fast, accurate and iterative design space exploration, using feedbacks from lower to higher abstraction layers and enabling physical design parameters to influence the system level design choices. [In recent years, the industry focus has been put on 3D technology as it provides numerous opportunities for building better systems. The number of functions in the system can be extended beyond the near term capabilities of traditional 2D scaling. 3D resolves the interconnect performance limitations because long lateral wires can be replaced with much shorter connections, significantly reducing related RC delay and buffering cost. 3D integration also supports the heterogeneous integration of components in dedicated technologies improving performance/power/cost metrics. Besides classical system-level design challenges, 3D design also involves additional degrees of freedom: 1. Partitioning of the design across multiple tiers; e.g., RF on logic; DRAM on logic, MEMS on logic, etc.; use of an existing die vs. a new die; 2. Selection of process technology per tier; DRAM vs. CMOS, CMOS65 vs. CMOS45, etc.; 3. The choice of the 3D interconnect. A substantial variety of 3D-Stacked Integrated Circuits (3D-SICs) schemes have been proposed. Variations across different schemes occur in terms of via geometry and pitch, via pitch, via stacking method (face-to-face or back-to-face), and bonding method (e.g., oxide bonding vs. fusion bonding). Different stacking schemes imply different electrical characteristics for the 3D interconnects. In this work we develop new design methodology and the corresponding EDA tool chain enabling fast design space exploration for emerging heterogeneous 3D-SICs using Through Silicon Vias (TSV) for inter-die connexions. The proposed framework, called PATHFINDING FLOW, allow designers to quickly evaluate many trade-offs between different system level design choices (e.g. functional partitioning, micro-architecture configuration of the functional blocks, interconnect topology and configuration etc.), physical design options (e.g. packaging strategies) and/or technology options (e.g. different technology nodes, threshold voltages, etc.) and understand their impact on typical design parameters such as cost, performance and power. The proposed framework is based on existing state-of-the-art System Level Exploration tools, High-Level Synthesis (HLS) tools (for both processing and communication) and Virtual Prototyping. Different tools have been integrated in one, unique and automated environment. The resulting framework allows fast, accurate and iterative design space exploration, using feedbacks from lower to higher abstraction layers and enabling physical design parameters to influence the system level design choices.]



disciplines et mots clés déclarés


Electronique et électrotechnique

electronique/microélectronique